1. Field of the Invention
This invention relates to the fabrication of integrated circuits by molecular beam etching.
2. Description of the Related Art
Integrated circuits are commonly fabricated by building up successive layers of materials on a silicon substrate. In the so-called "patterning" step, a resist pattern is established on a layer and those portions of the layer not coated with the resist are etched away, leaving the etched areas open for the deposition of additional materials. A cross-section of a portion of a typical semiconductor wafer at an intermediate stage of fabrication is illustrated in FIG. 1. A relatively thick bulk silicon substrate 2 is coated with a thin insulating layer 4 of silicon dioxide (SiO.sub.2), typically about 1,000 Angstroms (0.1 micron) thick. Layer 4 is covered with a polysilicon layer 6, which is typically in the order of 1 micron thick. A resist pattern 8 is then formed on the polysilicon layer, leaving gaps 10 in the resist layer through which the underlying polysilicon can be etched away.
In general, either liquid or gaseous etchants are used to remove the polysilicon underlying the gaps in the resist, each approach having its particular advantages and disadvantages. Since the present invention involves a gaseous or dry etching system, the discussion will focus primarily on this type of etching.
Assume that the polysilicon area 12, shown in cross-hatched lining in an opening through the resist layer, is to be etched away. Ideally, the etching process should satisfy at least the following three criteria:
(1) The etching should exhibit anisotropy. This means that the side walls of the etched area should be essentially vertical, as indicated by walls 14. Undercutting of the resist layers, as indicated by dashed line 16, should be avoided.
(2) The etching should exhibit selectivity. This means the etching process should extend to, but not go beyond, the interface between the polysilicon layer 6 and the thin SiO.sub.2 layer 4. The etching should not extend appreciably into the SiO.sub.2 layer, an undesirable situation indicated by dashed line 18.
(3) The etch rate should be reasonably fast to achieve a high throughput of wafers and a correspondingly efficient production rate.
With liquid etching, anisotropy normally cannot be achieved except for one limited crystal lattice structure. With gas etching, which is performed in a vacuum chamber, there is normally a trade-off between anisotropy and selectivity, and the etch rates are not particularly fast.
At present, anisotropic etching is accomplished either in plasma reactors operating in the reactive ion etching (RIE) mode, or in ion milling machines with reactive gases to give reactive ion beam etching (RIBE). Each of these methods has been found to produce specific etch rates below about 3,000 Angstroms per minute. With RIE the surface to be treated is immersed in a plasma consisting of chemically reactive radicals and ions from a parent gas. The relative amounts of ions and radicals cannot be independently controlled in a plasma reactor, resulting in an etching process which requires compromises. To achieve anisotropy, it is necessary to operate at low pressure with a low concentration of reactive species, further reducing the etch rate. The RIE technique is described in an article by C. J. Mogab and H. J. Levenstein, J. Vac. Sci. Technol. 17, page 721 (1980).
Reactive ion beam etching (RIBE) is also relatively slow because the current density of ions (at most 1 mA/cm..sup.2 at energies below 1000 eV) is too low at energies low enough to avoid radiation damage. With RIBE a plasma formed from ions and chemical radicals is directed at the surface to be treated. The addition of a beam of reactive molecules such as C1.sub.2 or NF.sub.3 can increase the etch rate, but bleeding reactive gases into the RIBE system raises the background pressure and scatters the ion beam unless the reactive species is supplied as a well-formed molecular beam. To accommodate both beams, the ion beam has typically been directed at the wafer along an axis perpendicular to the wafer surface, while the reactive beam has been applied at an angle to the wafer surface. The angular reactive beam, however, creates a "shadow" along the wafer surface at the edge of each resist layer, causing the polysilicon layer to be under-etched in the shadow region but undercutting the resist in the region opposite the shadow. While conceptually the ion and reactive beams might be manipulated so that both are directed perpendicular to the wafer, as a practical matter the neutral reactive beam is not subject to deflection by electromagnetic fields, and it is very difficult to successfully steer the wide area ion beams (2.5-15 cm. diameter) used in RIBE. The RIBE technique is described in the following articles: D. F. Downey, W. R. Bottoms and P. R. Hanley, Solid State Technol., February 1981, page 121; Y. Horiike and M. Shibagaki, Jpn. J. Appl. Phys. 18, page 2309 (1979); D. M. Brown, B. A. Heath, T. Coutumas and G. R. Thompson, Appl. Phys. Lett. 15, page 159 (1980); J. M. E. Harper, J. J. Cuomo, P. A. Leary, G. M. Summa, H. R. Kaufman and F. J. Bresnoch, J. Electrochem. Soc. 128, page 1077 (1981).
Another problem associated with both RIE and RIBE is that, because the entire wafer is flooded with the molecular particles, the detection of the "end point" (e.g., the polysilicon-SiO.sub.2 interface in the example given above) is ambiguous. Wafer yield can be significantly reduced because of either over or under etching.